Field of the Invention
The present invention relates to methods and apparatus for semiconductor wafer metrology, for example, in the manufacture of devices by lithographic techniques. More specifically, it relates to optimization procedures for arrangement of a target, and of a target so arranged.
Background Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In order to monitor the lithographic process, parameters of the patterned substrate are measured. Parameters may include, for example, the overlay error between successive layers formed in or on the patterned substrate and critical linewidth of developed photosensitive resist. This measurement may be performed on a product substrate and/or on a dedicated metrology target. Metrology targets (or marks) may comprise, for example, combinations of horizontal and vertical bars, forming for example periodic structures such as gratings.
There are various techniques for making measurements of the microscopic structures formed in lithographic processes, including the use of scanning electron microscopes and various specialized tools. A fast and non-invasive form of specialized inspection tool is a scatterometer in which a beam of radiation is directed onto a target on the surface of the substrate and properties of the scattered or reflected beam are measured.
Various forms of scatterometers have been developed for use in the lithographic field. These devices direct a beam of radiation onto a target and measure one or more properties of the scattered radiation—e.g., intensity at a single angle of reflection as a function of wavelength; intensity at one or more wavelengths as a function of reflected angle; or polarization as a function of reflected angle—to obtain a “spectrum” from which a property of interest of the target can be determined. Determination of the property of interest may be performed by various techniques: e.g., reconstruction of the target structure by iterative approaches such as rigorous coupled wave analysis or finite element methods; library searches; and principal component analysis.
Examples of known scatterometers include angle-resolved scatterometers of the type described in US2006033921A1 and US2010201963A1. The targets used by such scatterometers are relatively large, e.g., 40 μm by 40 μm, gratings and the measurement beam generates a spot that is smaller than the grating (i.e., the grating is underfilled). This simplifies mathematical reconstruction of the target as it can be regarded as infinite.
To limit the real-estate consumption for metrology purposes on each production wafer, metrology and alignment targets are being reduced in size. For example, target-sizes for overlay metrology range between 20×20 μm2 to 10×10 μm2. The use of smaller target-sizes is under study. Typically such targets are measured using “dark field” scatterometry in which the zeroth order of diffraction (corresponding to a specular reflection) is blocked, and only one or more higher orders are processed to create a gray scale image of the target (i.e. ‘dark field’ image). Diffraction-based overlay using this dark field technique enables overlay measurements on smaller targets, and is known as micro-diffraction based overlay (μDBO). Examples of dark field metrology can be found in international patent applications WO2009/078708, WO2009/106279, WO2013178422 and WO2013/143814. Further developments of the technique have been described in published patent publications US20110027704A, US20110043791A, US20120044470A US20120123581A, US20130258310A and US20130271740A; and in the U.S. patent applications 61/652,552 and 61/803,673. These targets can be smaller than the illumination spot and may be surrounded by product structures on a wafer. Thus, ‘composite’ targets (e.g. target comprising a plurality of individual grating portions of different overlay biases) can be entirely measured in one image. Therefore, the grating edges are also visible in the gray scale images of the target. The grating edges often present intensity levels that deviate from the average grating intensity (referred to herein as ‘edge effects’).
After image post processing (e.g. pattern recognition), regions-of-interest (ROIs) within each individual grating may be identified in the dark field image. An average grating intensity can be calculated for each ROI, while excluding the influence of the edge effects. Asymmetry of the grating structure, and hence overlay error, can then be inferred from average intensities.
As such, the average grating intensity is inferred from, for instance, a few CCD image sensor pixels (i.e. size of the selected ROIs on the sensor), corresponding to the center of the grating in the dark field image.
A current μDBO target design/layout is based on infinitely large gratings. Gratings features such as the line space dimensions, pitch, sub-segmentation etc., are optimized, depending on the application. The gratings are positioned around predefined grating centers in a region defining the target.
Computational lithography modeling (e.g. Litho-OPC, where OPC stands for optical proximity correction) is commonly used to design and optimize printable targets. The target layout may include sub-resolution ‘assist features’ (i.e. not detected by the sensor) to improve the dark field image resolution. These assist features may be located at arbitrary positions around ‘detectable’ target structures (e.g. around one of the target gratings and/or around wafer locations allocated to contain targets, also called target region) and can be used by the pattern recognition process. By generating ‘empty’ regions around the ‘detectable’ target structures, the pattern recognition process can then identify the position of the ROI with substantially greater accuracy than using only, for example, the edges of the grating. By providing recognizable assist features which are two, three or more times as numerous as for instance the boundaries of the target gratings, the accuracy of recognizing the ROI can be increased. However, the nominal region defining the target is consequently enlarged, for example, from 10×10 μm2 to 12×12 μm2 for μDBO targets.
It is desirable to provide an improved target design methodology and consequently improved targets.